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| LTC1659 12-Bit Rail-to-Rail Micropower DAC in MSOP Package DESCRIPTION The LTC(R)1659 is a single supply, rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC) in an MSOP package. It includes a rail-to-rail output buffer amplifier and an easy-to-use 3-wire cascadable serial interface. The LTC1659 output swings from 0V to REF. The REF input can be tied to VCC which can range from 2.7V to 5.5V. This allows a rail-to-rail output swing from 0V to VCC. The LTC1659 draws only 250A from a 5V supply. Its guaranteed 0.5LSB maximum DNL makes the LTC1659 excel in calibration, control and trim/adjust applications. The low power supply current and the small MSOP package make the LTC1659 ideal for battery-powered applications. , LTC and LT are registered trademarks of Linear Technology Corporation. FEATURES s s s s s s s s s s s 8-Lead MSOP Package 12-Bit Resolution Supply Operation: 3V to 5V Buffered True Rail-to-Rail Voltage Output Output Swings from 0V to VREF VREF Can Tie to VCC Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface Power-On Reset Clears DAC to 0V 3-Wire Cascadable Serial Interface Maximum DNL Error: 0.5LSB Low Cost APPLICATIONS s s s s Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones TYPICAL APPLICATION Functional Block Diagram: 12-Bit Rail-to-Rail DAC 2.7V TO 5.5V 8 VCC 2 DIN 1 CLK P 3 CS/LD 12-BIT SHIFT REG AND DAC LATCH 6 REF 0.5 + 12-BIT DAC VOUT 7 - DNL ERROR (LSB) RAIL-TO-RAIL VOLTAGE OUTPUT 4 DOUT TO OTHER DACS POWER-ON RESET GND 5 1659 TA01 U U U Differential Nonlinearity vs Input Code 0 -0.5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE 1659 TA02 1 LTC1659 ABSOLUTE MAXIMUM RATINGS VCC to GND ...............................................- 0.5V to 7.5V Logic Inputs to GND .................................- 0.5V to 7.5V VOUT ............................................... - 0.5V to VCC + 0.5V Maximum Junction Temperature .......................... 125C Storage Temperature Range ................. - 65C to 150C Operating Temperature Range LTC1659CS8 ........................................... 0C to 70C LTC1659IS8 ....................................... - 40C to 85C LTC1659CMS8 (Note 1) .......................... 0C to 70C Lead Temperature (Soldering, 10 sec).................. 300C PACKAGE/ORDER I FOR ATIO TOP VIEW CLK 1 DIN 2 CS/LD 3 DOUT 4 8 7 6 5 VCC VOUT REF GND ORDER PART NUMBER LTC1659CS8 LTC1659IS8 S8 PART MARKING 1659 1659I CLK DIN CS/LD DOUT 1 2 3 4 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125C, JA = 150C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 2.7V to 5.5V, VOUT unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted. SYMBOL DAC Resolution Monotonicity DNL INL VOS VOSTC VFS VFSTC Differential Nonlinearity Integral Nonlinearity Offset Error Offset Error Temperature Coefficient Full-Scale Voltage Full-Scale Voltage Temperature Coefficient TA = 25C, REF = 4.096V (Note 6) REF = 4.096V (Note 6) q q q PARAMETER CONDITIONS VREF VCC - 0.1V (Note 2) VREF VCC - 0.1V (Note2), TA = 25C VREF VCC - 0.1V (Note 2) Measured at Code 20, TA = 25C Measured at Code 20 2 U U W WW U W TOP VIEW 8 7 6 5 VCC VOUT REF GND ORDER PART NUMBER LTC1659CMS8 MS8 PART MARKING LTCK MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 206C/W MIN 12 12 TYP MAX UNITS Bits Bits q q q 0.5 5.0 5.5 12 18 15 4.070 4.060 4.095 4.095 10 4.120 4.130 LSB LSB LSB mV mV V/C V V ppm/C LTC1659 ELECTRICAL CHARACTERISTICS VCC = 2.7V to 5.5V, VOUT unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted. SYMBOL VCC ICC PARAMETER Positive Supply Voltage Supply Current Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND Output Line Regulation AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Reference Input RIN REF Digital I/O VIH VIL VOH VOL VIH VIL VOH VOL ILEAK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 5V VCC = 5V VCC = 5V, IOUT = - 1mA, DOUT Only VCC = 5V, IOUT = 1mA, DOUT Only VCC = 3V VCC = 3V VCC = 3V, IOUT = - 1mA, DOUT Only VCC = 3V, IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 7) q q q q q q q q q q CONDITIONS For Specified Performance (Note 5) VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 Input Code = 4095, VCC = 4.5V to 5.5V (Note 3) (Notes 3, 4) to 0.5LSB q q q MIN 2.7 TYP MAX 5.5 UNITS V A mA mA LSB/V V/s s nV * s Power Supply 240 70 65 40 0.1 0.5 1.0 14 0.3 q 450 120 120 150 1.5 Op Amp DC Performance q q q REF Input Resistance REF Input Range (Notes 6, 7) 17 0 2.4 28 40 VCC k V V q 0.8 VCC - 1.0 0.4 2.0 0.6 VCC - 0.7 0.4 10 10 V V V V V V V A pF 3 LTC1659 ELECTRICAL CHARACTERISTICS VCC = 2.7V to 5.5V, VOUT unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted. SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 t2 t3 t4 t5 t6 t7 t8 t9 PARAMETER DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low (Note 7) (Note 7) (Note 7) (Note 7) (Note 7) CLOAD = 15pF (Note 7) (Note 7) (Note 7) (Note 7) (Note 7) (Note 7) CLOAD = 15pF (Note 7) CONDITIONS q q q q q q q q q MIN 40 0 40 40 50 40 20 5 20 60 0 60 60 80 60 30 10 30 TYP MAX UNITS ns ns ns ns ns ns ns Switching (VCC = 4.5 to 5.5V) 150 ns ns ns ns ns ns ns ns ns Switching (VCC = 2.7 to 5.5V) q q q q q q q q q 220 ns ns The q denotes specifications which apply over the full operating temperature range. Note 1: The LTC1659CMS8 is designed, characterized and expected to meet industrial temperature limits, but is not tested at - 40C and 85C. Consult factory for guaranteed I-grade MSOP parts. However, these parts are guaranteed for commercial temperature limits of 0C to 70C. Note 2: Nonlinearity is defined from code 20 to code 4095 (full scale). See Applications Information. Note 3: Load is 5k in parallel with 100pF. Note 4: DAC switched between all 1s and the code corresponding to VOS for the part. Note 5: Digital inputs at 0V or VCC. Note 6: VOUT can only swing from (GND + VOS) to (VCC - VOS) when output is unloaded. Note 7: Guaranteed by design. Not subject to test. 4 LTC1659 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) 5 4 3 DNL ERROR (LSB) 0.5 OUTPUT PULL-DOWN VOLTAGE (V) INL ERROR (LSB) 2 1 0 -1 -2 -3 -4 -5 0 512 1824 1536 2048 2560 3072 3584 4095 CODE LTC1659 * TPC01 Supply Headroom for Full Output Swing vs Load Current 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 LOAD CURRENT (mA) 15 LTC1659 * TPC04 SUPPLY CURRENT (mA) VOUT < 1 LSB CODE = ALL 1s VOUT = 4.095V 125C 25C 1.6 1.2 0.8 0.4 SUPPLY CURRENT (A) VCC - VOUT (V) UW -55C Differential Nonlinearity (DNL) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 512 1024 1536 2048 2560 3072 3584 4095 CODE LTC1659 * TPC02 Minimum Output Voltage vs Output Sink Current CODE = ALL ZEROS VCC = 5V 0 125C 25C -55C -0.5 0 5 10 OUTPUT SINK CURRENT (mA) 15 LTC1659 * TPC03 Supply Current vs Logic Input Voltage 300 2 VCC = 5V 290 280 270 260 250 Supply Current vs Temperature VCC = 5.5V VCC = 5.0V VCC = 4.5V 240 230 0 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 5 220 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) LTC1659 * TPC06 LTC1659 * TPC05 5 LTC1659 PIN FUNCTIONS CLK (Pin 1): Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. DIN (Pin 2): Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. CS/LD (Pin 3): Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output and the CLK is disabled internally. DOUT (Pin 4): Output of the Shift Register which Becomes Valid on the Rising Edge of the Serial Clock. GND (Pin 5): Ground. REF (Pin 6): Reference Input. This pin can be tied to VCC. The output will swing from 0V to REF. The typical input resistance is 28k. VOUT (Pin 7): Buffered DAC Output. VCC (Pin 8): Positive Supply Input. 2.7V VCC 5.5V. Requires a bypass capacitor to ground. BLOCK DIAGRA CLK 1 DIN 2 12-BIT SHIFT REGISTER CS/LD 3 DOUT 4 6 W U U U 8 VCC LD DAC REGISTER 12-BIT DAC + 7 VOUT - POWER-ON RESET 6 REF 5 GND 1659 BD LTC1659 TI I G DIAGRA CLK t9 DIN B0 PREVIOUS WORD B11 MSB B10 B1 B0 LSB CS/LD DOUT B11 PREVIOUS WORD DEFI ITIO S Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB Where VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/4095)]/LSB Where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/4096 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. W t1 t2 t6 t7 t4 t3 t8 t5 B10 B1 B0 B11 CURRENT WORD 1659 TD U U UW 7 LTC1659 OPERATIO Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The CLK is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The buffered output of the 12-bit shift register is available on the DOUT pin which swings from GND to VCC.Multiple LTC1659s may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip, while the CLK and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all of them simultaneously. 8 U Voltage Output The LTC1659's rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 300mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40 when driving a load to the rails. The output can drive 1000pF without going into oscillation. The output swings from 0V to the voltage at the REF pin, i.e., there is a gain of 1 from the REF to VOUT. Please note if REF is tied to VCC the output can only swing to (VCC - VOS). See Applications Information. LTC1659 APPLICATIONS INFORMATION Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 1(b). Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown is Figure 1(c). No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. OUTPUT VOLTAGE 0 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1659 F01 Figure 1. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC U W U U VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC 2048 INPUT CODE (a) 4095 9 LTC1659 TYPICAL APPLICATION 12-Bit, 3V to 5V Single Supply, Rail-to-Rail Voltage Output DAC 2.7V TO 5.5V PACKAGE DESCRIPTION 0.007 (0.18) 0.021 0.006 (0.53 0.015) * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 10 U U 0.1F DIN VCC P CLK LTC1659 CS/LD DOUT TO NEXT DAC FOR DAISY-CHAINING GND REF VOUT OUTPUT 0V TO REF 1659 TA03 Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 0.004* (3.00 0.102) 8 76 5 0.192 0.004 (4.88 0.10) 0.118 0.004** (3.00 0.102) 1 0.040 0.006 (1.02 0.15) 0 - 6 TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP 23 4 0.034 0.004 (0.86 0.102) 0.006 0.004 (0.15 0.102) MSOP (MS8) 1197 LTC1659 PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 - 0.197* (4.801 - 5.004) 8 7 6 5 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP 0.053 - 0.069 (1.346 - 1.752) 2 3 4 0.004 - 0.010 (0.101 - 0.254) 0.016 - 0.050 0.406 - 1.270 0.014 - 0.019 (0.355 - 0.483) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE SO8 0996 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC1659 TYPICAL APPLICATION Digitally Programmable Current Source 5V VS + 6V TO 100V FOR RL 50 CLK P DIN CS/LD RELATED PARTS PART NUMBER LTC1257 LTC1446/LTC1446L LTC1448 LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1456 LTC1458/LTC1458L DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V Dual 12-Bit VOUT DACs in SO-8 Package Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 5V, Low Power Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U 0.1F VCC REF VOUT RL IOUT = DIN * 5 0mA TO 10mA 4096 * RA LTC1659 GND + LT1077 Q1 2N3440 - RA 510 5% 1659 TA04 1659f LT/TP 0498 4K * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1997 |
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